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FIQ-RoT04B Chiplet RoT Secure Core

FortifyIQ Chiplet SCA/FI protected RoT with Post-Quantum Security

Heterogeneous chiplet-based architectures require a trusted hardware anchor to ensure secure integration, firmware integrity, and device identity. FortifyIQ’s Chiplet RoT is a compact, energy-efficient security IP core designed specifically for chiplet ecosystems, enabling secure boot, attestation, and identity management across multi-die systems.

Powered by FortifyIQ’s proprietary cryptographic engine, the Chiplet RoT supports both classical and post-quantum algorithms while incorporating patented countermeasures against side-channel and fault injection attacks. Engineered for flexible die-to-die interfaces and optimized for chiplet interconnect standards, it provides certifiable, quantum-resistant security for next-generation modular SoCs.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • Secure Communications
  • Network Devices

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library 
  • Security documentation

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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