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FIQ-RoT02F Secure RoT Core for Data Centers

FortifyIQ Secure RoT with Post-Quantum Cryptography

Datacenter-class SoCs such as CPUs, GPUs, DPUs, and NVMe controllers require a trusted hardware foundation to ensure firmware integrity, secure boot, and confidential computing. Building on the open-source Caliptra Root of Trust (RoT), FortifyIQ extends its capabilities by replacing the entire cryptographic subsystem with a proprietary engine that supports both classical and post-quantum algorithms.

Equipped with FortifyIQ’s efficient, patented countermeasures against side-channel and fault injection attacks, the RoT delivers robust, certifiable cryptography with quantum-resistant security. It enables secure attestation, identity management, and protection against advanced physical threats, making it a forward-looking solution for the next generation of datacenter-class devices.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness
  • RAM/ROM Firmware Support

Applications

  • Data Centers
  • Secure Networking Equipment
  • Secure Communications
Technical Overview

FortifyIQ’s Secure RoT builds on the open-source Caliptra Root of Trust (RoT) project, enhancing it with a proprietary cryptographic subsystem that supports both classical and post-quantum algorithms. The subsystem implements asymmetric and symmetric cryptography, including ECDH, ECDSA, RSA, AES, SHA-2/3, HMAC, and NIST-approved post-quantum signature schemes, ensuring compliance with FIPS 186-5, SP 800-56A, and NIST PQC standards.

The architecture integrates FortifyIQ’s patented, high-efficiency countermeasures against side-channel and fault injection attacks, such as masking, input randomization, integrity checks, error-detection codes, memory scrambling, and timing-invariant logic. These protections, deployed across all FortifyIQ products, provide resilience against advanced physical threat models. As with Caliptra, the RoT secures datacenter-class SoCs by verifying firmware integrity, enabling secure boot, attestation, identity management, and confidential computing for CPUs, GPUs, DPUs, and NVMe controllers. The design supports flexible integration into ASICs and SoCs through standard interfaces, and comes with HAL and software libraries to simplify deployment.

Validated against advanced attack vectors, the Secure RoT is engineered to meet or exceed all assurance levels of FIPS 140-3 and Common Criteria, ensuring long-term, certifiable security for next-generation datacenter-class devices.

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-BOX01C  – Compact accelerator for asymmetric cryptography and AES
  • FIQ-BOX03B  – Hybrid Crypto Box IP Core with Classical and Post-Quantum Cryptography for Embedded Systems
  • FIQ-BOX04F  – High-Performance Hybrid Crypto Box IP Core for Quantum-Ready Secure Systems
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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