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FIQ-PKA03B RSA Accelerator

SCA/FI-Protected RSA Accelerator

FortifyIQ’s RSA Accelerator delivers high-performance modular exponentiation for RSA-based public key cryptography, while incorporating advanced protections against side-channel analysis (SCA) and fault injection (FI) attacks. Optimized for secure key generation, encryption, decryption, and digital signature operations, the core ensures robust cryptographic processing without compromising efficiency.

The design integrates lightweight yet highly effective physical attack countermeasures at the RTL level, making the accelerator suitable for both certification-driven applications and security-critical environments. Supporting variable key lengths up to 4096 bits, it provides scalability for a broad spectrum of use cases, from embedded systems to enterprise-grade secure communications.

Compliant with FIPS 140-3 and Common Criteria requirements across all levels, the FortifyIQ RSA Accelerator balances strong security with performance, offering a trusted foundation for secure boot, key management, and authentication in modern hardware platforms.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
Technical Overview

The FortifyIQ RSA Accelerator is a high-performance hardware IP core designed to efficiently execute RSA cryptographic operations while providing advanced protection against physical attacks. It supports key lengths up to 4096 bits, enabling secure encryption, decryption, digital signatures, and key exchange protocols for a wide range of applications, from embedded devices to high-end secure communication systems.

Instead of relying on traditional Montgomery multiplication, the core integrates a more efficient patented modular arithmetic algorithm, significantly accelerating modular exponentiation while reducing computational overhead. This innovative approach allows the RSA Accelerator to deliver outstanding performance with optimized area and power usage. In parallel, the architecture incorporates advanced countermeasures against side-channel analysis (SCA) and fault injection (FI) attacks, implemented at the RTL level to remain independent of process technology and integration context. These protections ensure strong resistance to physical threats while maintaining computational efficiency.

The RSA Accelerator is designed in line with Common Criteria and FIPS 140-3 requirements, making it ideal for secure boot, authentication, and key management systems. By combining strong mathematical security with a patented high-performance arithmetic engine and proven physical protection, it provides a trusted solution for security-critical applications.

External Dependencies

  • Requires an external cryptographically secure random number generator (CSPRNG)
  • Requires an external hash function to enable ECDSA operations

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-PKA01C – Compact version of FIQ-PKA01B
  • FIQ-PKA04C – Compact RSA signature verification core
  • FIQ-BOX01C – Compact accelerator for asymmetric cryptography and AES
  • FIQ-PQC04B – Accelerator for Classical and Post-Quantum asymmetric cryptography
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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