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FIQ-HMAC03B Zero Leakage HMAC-SHA256 Secure Core

High-Security SHA-2/HMAC Core with Zero Side-Channel Leakage (SHA-224/256 Only)

FortifyIQ’s High-Security SHA-2/HMAC IP core delivers formally proven zero side-channel leakage for SHA-2-224 and SHA-2-256 hashing and HMAC, making it ideal for security-critical embedded systems where resistance to physical attacks is non-negotiable. Targeted at applications willing to trade off performance and area for uncompromising protection, this RTL-level design is built with mathematically verified countermeasures against side-channel analysis. As with all FortifyIQ products, the protection is implementation-agnostic and integration-friendly, supporting systems aiming for the highest levels of Common Criteria and FIPS 140-3 certification.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s High-Security SHA-2/HMAC IP core is a cryptographic accelerator designed for security-critical applications that demand mathematically guaranteed protection against side-channel leakage. The core supports SHA-2-224 and SHA-2-256, along with their corresponding HMAC modes, making it ideal for secure boot, firmware authentication, digital signatures, and cryptographic protocols where physical attack resistance is paramount.

This core is built around a hardened architecture that integrates formally proven countermeasures against side-channel analysis (SCA), ensuring zero exploitable leakage even under advanced power analysis techniques. These protections are applied entirely at the RTL level using algorithmic masking and are backed by formal verification tools and side-channel simulators. The protection is layout-independent, ensuring consistent security across different process nodes, ASICs, and FPGAs. While the design introduces some performance and area overhead compared to conventional implementations, it provides security protection that exceeds the highest levels of Common Criteria and FIPS 140-3 requirements.

The core integrates easily via standard APB or AHB interfaces, with a straightforward control structure and minimal integration overhead. FortifyIQ’s High-Security SHA-2/HMAC core (224/256-bit only) offers unmatched physical security for mission-critical applications with strict assurance requirements.

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library
  • Security documentation

Related Products

  • FIQ-HMAC01F – Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
  • FIQ-HMAC02F – High-Performance SHA-2/HMAC Accelerator with Full SHA-2 Family Support and Low Latency SCA/FI Protection
  • FIQ-HMAC04B – High-Security SHA-2/HMAC Core with Zero Side-Channel Leakage Guarantee
  • FIQ-BOX02B – Versatile Crypto Box IP Core with Robust SCA/FI Protections for Balanced Embedded Systems
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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