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FIQ-HMAC01F HMAC-SHA256 Secure Core

Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection

FortifyIQ’s SHA-2/HMAC IP core delivers high-speed, hardware-accelerated SHA-2-224/256 hashing and HMAC computation, optimized for secure embedded systems and cryptographic protocols. Designed for efficiency and low latency, the core is ideal for use in secure boot, firmware authentication, TLS, and MAC generation. As with all FortifyIQ products, it features highly efficient yet low-latency protection against side-channel and fault injection attacks, implemented at the RTL level to ensure consistent defense across ASIC and FPGA platforms. Compact, secure, and performance-oriented, this core is built for systems targeting FIPS 140-3 and Common Criteria certification.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

Related Products

FIQ-HMAC02F

High-Performance SHA-2/HMAC Accelerator with Full SHA-2 Family Support and Low Latency SCA/FI Protection

FIQ-HMAC03B

High-Security SHA-2/HMAC Core with Zero Side-Channel Leakage (SHA-224/256 Only)

FIQ-HMAC04B

High-Security SHA-2/HMAC Core with Zero Side-Channel Leakage Guarantee

FIQ-BOX02B

Versatile Crypto Box IP Core with Robust SCA/FI Protections for Balanced Embedded Systems

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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