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FIQ-AES13T AES-XP-GCM-XTS Ultra-High-Performance Secure Core

High-Performance AES-GCM/XTS Core with Integrated SCA/FI Protection

FortifyIQ’s AES-GCM/XTS IP core delivers high-throughput encryption and decryption with support for both AES-GCM (for data in motion) and AES-XTS (for data at rest) modes, making it ideal for unified secure storage and communication applications. Built on a pipelined architecture optimized for performance, the core supports AES-128/256 and enables seamless switching between modes. It integrates RAMBAM, FortifyIQ’s RTL-level protection scheme, offering robust resistance to side-channel and fault injection attacks. Designed for systems targeting FIPS 140-3 and Common Criteria, this dual-mode core simplifies hardware design while delivering high speed, flexibility, and advanced physical security.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s AES-GCM/XTS IP core is a versatile, high-performance encryption and authentication engine that supports both AES-GCM and AES-XTS modes in a single unified architecture. This dual-mode design enables secure handling of both data in motion (via AES-GCM) and data at rest (via AES-XTS), making it ideal for applications such as storage encryption, secure communications, and embedded systems requiring both confidentiality and authentication.

Built on a deeply pipelined architecture, the core delivers multi-gigabit throughput with AES-128 and AES-256 key support. Mode selection is configurable at runtime, allowing efficient use of hardware resources and reducing system complexity by eliminating the need for separate GCM and XTS engines. The core includes a tightly integrated GHASH unit for high-speed GCM tag generation and verification, and supports sector-based tweak computation for XTS.

To address physical security threats, the core incorporates RAMBAM, FortifyIQ’s advanced protection scheme against side-channel analysis (SCA) and fault injection (FI) attacks. RAMBAM applies algorithmic countermeasures at the RTL level, including masking, redundancy, and ensuring protection without relying on layout-specific constraints. These protections are technology-agnostic and effective across ASICs and FPGAs.

The core supports standard interfaces such as AXI or AHB, with flexible configuration options and minimal integration overhead. It is engineered to support FIPS 140-3 and Common Criteria certification requirements. FortifyIQ’s AES-GCM/XTS Core offers a high-throughput, security-hardened, and integration-friendly solution for systems that require dual-mode encryption across storage and communication domains.

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library
  • Security documentation
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own
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