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FIQ-AES11T AES-XP-GCM Ultra-High-Performance Secure Core

Ultra-High-Performance AES-GCM Core with RAMBAM-Based SCA/FI Protection

FortifyIQ’s AES-GCM IP core delivers ultra-high-throughput authenticated encryption and decryption using a fully pipelined architecture, optimized for performance-critical applications such as secure networking, high-speed storage, and real-time communications. Supporting AES-128/256 in GCM mode, the core combines low latency with sustained multi-gigabit performance. It integrates RAMBAM, FortifyIQ’s advanced protection scheme that provides robust resistance to side-channel and fault injection attacks through algorithmic, RTL-level countermeasures. Designed for systems targeting FIPS 140-3 and Common Criteria, this core offers an ideal combination of performance, scalability, and advanced physical attack resistance for modern secure hardware platforms.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Secure Communications
  • Network Devices

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

Related Products

FIQ-AES12T

Ultra-High-Performance AES-XTS Core with RAMBAM-Based SCA/FI Protection

FIQ-AES13T

Ultra-High-Performance AES-GCM/XTS Core with Integrated SCA/FI Protection

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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