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FIQ-AES09F AES-SX-ULP-full Secure Core

High-Performance/Ultra Low Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection

FortifyIQ’s High-Throughput, Ultra Low Power AES IP core delivers AES-128/256 encryption-only with full support for ECB, CBC, CTR,  GCM, and XTS modes, optimized for maximum speed in secure, data-intensive systems. Its parallel multi-S-box architecture enables high throughput and low latency, ideal for storage encryption, secure networking, and real-time applications. The core integrates STORM, an ultra-low power lookup table-based side-channel protection scheme derived from  FortifyIQ’s RAMBAM architecture. STORM includes a formally proven guarantee of resistance against side-channel attacks (SCA) and is implemented entirely at the RTL level, ensuring layout-agnostic, technology-independent protection. Designed for systems targeting FIPS 140-3 and Common Criteria, this AES core offers a robust blend of performance, ultra-low power efficiency, flexibility, and certified-ready physical security for high-end embedded platforms.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s High-Throughput AES IP core is a high-performance while preserving low-power consumption, encryption-only hardware accelerator optimized for systems requiring fast and secure AES-128/256 encryption across all major modes, including ECB, CBC, CTR, GCM, and XTS. Designed for data-intensive environments such as secure networking, high-speed storage, automotive systems, and embedded security appliances, the core combines low latency with high throughput through a parallel architecture built on multiple protected S-boxes.

To meet advanced physical security needs, the core integrates STORM, a lookup table-based side-channel protection scheme derived from FortifyIQ’s RAMBAM architecture. STORM includes formally proven resistance to side-channel attacks (SCA). These protections are algorithmic, layout-independent, and implemented entirely at the RTL level, ensuring consistent effectiveness across different technology nodes, ASICs, and FPGAs.

The core supports standard system interfaces, such as AXI, AHB, and APB, with flexible configuration options and efficient key management. It includes a lightweight control interface, enabling easy integration in performance-sensitive SoCs and security subsystems.

Engineered to support FIPS 140-3 and Common Criteria certification efforts, FortifyIQ’s High-Performance AES Core provides an ideal solution for applications that demand maximum encryption speed, full-mode flexibility, and strong, provable physical security.

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library
  • Security documentation
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own
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