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FIQ-AES07C AES-SX-ULP-full Secure Core

Ultra-Low-Power AES Core with Proven SCA Protection for Constrained Devices

FortifyIQ’s Ultra-Low-Power AES IP core is a compact encryption engine optimized for deeply embedded and battery-powered systems where minimizing energy and silicon footprint is critical. Supporting AES-128 encryption in ECB mode, the core features a power-efficient, serialized architecture and integrates STORM, a lookup table-based side-channel protection scheme, derived from RAMBAM. STORM includes formally proven resistance against side-channel attacks (SCA) and incorporates fault injection (FI) countermeasures at the RTL level. Entirely algorithmic and implementation-agnostic, this silicon-proven core is ideal for secure IoT endpoints, wearables, and smart sensors aiming to meet FIPS 140-3 and Common Criteria requirements under tight power and area constraints.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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