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FIQ-AES05F AES-SX-GCM-XTS Secure Core

High-Performance AES Encryption Core with GCM/XTS Support and Advanced SCA/FI Protection

FortifyIQ’s High-Performance AES Encryption Core is a fast, encryption-only hardware accelerator built for systems that demand secure and authenticated data processing at scale. Supporting AES-128/256 encryption in ECB, CBC, CTR, GCM, and XTS modes (encryption only), the core delivers high throughput for data-in-motion and data-at-rest applications, including storage encryption and secure communications. Based on a 20 S-box architecture, it combines speed with strong physical security using FortifyIQ’s RAMBAM protection scheme, which provides advanced side-channel and fault injection resistance at the RTL level. Silicon-proven and validated by a Common Criteria accredited lab, the core is engineered for use in systems targeting FIPS 140-3 and Common Criteria certification.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Payment Systems
  • Secure Communications
  • Network Devices

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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