Protecting Quantum Era Cryptography. Today.
Protecting Quantum Era Cryptography. Today.
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FIQ-AES02B AES-SX Secure Core

Balanced AES Core with Multi-Mode Support and Advanced SCA/FI Protection

FortifyIQ’s Balanced AES IP core is a compact yet capable cryptographic accelerator designed for embedded systems with moderate performance and resource requirements. Supporting AES-128/256 encryption and decryption in all standard modes, including ECB, CBC, and CTR  (excluding GCM and XTS), the core delivers flexible and efficient data protection. Built on a four-S-box architecture for improved throughput, it features robust side-channel and fault-injection countermeasures, based on the innovative RAMBAM protection scheme. Applied at the RTL level and validated by a Common Criteria accredited lab, the core is silicon-proven and ready for use in applications targeting FIPS 140-3 and Common Criteria certification. Ideal for secure boot, encrypted storage, and communication protocols in balanced embedded devices.

Features

  • Efficient Performance
  • SCA/FIA Protections, DFA optional 
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

Related Products

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FIQ-BOX02B

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FIQ-AES08B

Ultra-Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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