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Protecting Quantum Era Cryptography. Today.
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FIQ-AES01C AES-SX Secure Core

Compact AES Encryption Core with Robust SCA/FI Protection for Constrained Devices

FortifyIQ’s Compact AES IP core is an ultra-lightweight hardware accelerator optimized for resource-constrained embedded systems that require secure encryption with minimal area and power consumption. Supporting AES-128 encryption in ECB mode only, the design focuses on essential cryptographic functionality for devices such as smart sensors, RFID, and secure tokens. Despite its small footprint, the core integrates advanced, implementation-agnostic protections against side-channel analysis (SCA) and fault injection (FI) at the RTL level, ensuring strong physical attack resistance. Built for easy integration and hardware-level assurance, this core is engineered to support certification under FIPS 140-3 and Common Criteria, making it a trusted choice for compact, high-assurance secure applications.

Features

  • Efficient Performance
  • SCA/FIA Protections, DFA optional 
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

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FIQ-AES02B

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FIQ-AES07C

Ultra-Low-Power AES Core with Proven SCA Protection for Constrained Devices

FIQ-AES08B

Ultra-Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection

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FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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