FIQ-PKA04C RSA Signature Verification Accelerator

Compact RSA Signature Verification Accelerator for Constrained Devices

RSA signature verification is widely used in secure boot and code authentication, yet it can strain the limited computational resources of low-power embedded systems. FortifyIQ’s FIQ-PKA04C is a compact and efficient RSA verification IP core optimized for SoC integration in resource-constrained environments. Designed specifically for public-key operations, it requires no countermeasures against side-channel or fault injection attacks. Supporting RSA-4096 with fast modular arithmetic, FIQ-PKA04C enables standards-compliant cryptographic verification with minimal area and power consumption, ideal for secure applications that demand lightweight, high-assurance public-key validation.

Features

  • Efficient Performance
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

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Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library 
  • Security documentation

Related Products

FIQ-PKA02B

Balanced ECC accelerator

FIQ-BOX01C

Compact accelerator for asymmetric cryptography and AES

FIQ-PQC04B

Accelerator for Classical and Post-Quantum asymmetric cryptography

Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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