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FIQ-BOX04F Crypto Box Toolset Secure Accelerator

High-Performance Hybrid Crypto Box IP Core for Quantum-Ready Secure Systems

FortifyIQ’s High-Performance Hybrid Crypto Box IP core delivers maximum cryptographic throughput by combining classical asymmetric (RSA, ECC), symmetric (AES), and hashing (SHA-2/HMAC) engines with a dedicated post-quantum accelerator supporting ML-KEM (Kyber) and ML-DSA (Dilithium). Designed for performance-critical systems without tight area or power limitations, this IP enables ultra-fast key exchange, digital signatures, and secure data processing. All cryptographic engines are hardened against side-channel and fault injection attacks, including algorithmic RTL-level protections for AES and SHA. With native support for hybrid protocols, secure boot, and firmware authentication, this Crypto Box is ideal for high-assurance platforms that require long-term, quantum-safe security at scale.

Features

  • Full Elliptic Curve Support
  • RSA-2048, RSA-3072, RSA-4096
  • ML-KEM (Kyber) and ML-DSA (Dilithium)
  • AES-128, AES-192, AES-256
  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • Data Centers
  • Secure Networking Equipment
  • Secure Communications
  • High-end Edge Computing
  • Automotive ECUs
  • Defense, Aerospace, and Military-grade Embedded Systems
  • Embedded and Industrial Control
  • IoT Devices
  • Payment Systems
  • Authentication Tokens
Technical Overview

FortifyIQ’s High-Performance Hybrid Crypto Box IP core is a comprehensive cryptographic accelerator built for systems requiring top-tier throughput, low latency, and future-proof cryptographic agility. It integrates classical public-key algorithms, high-speed symmetric encryption, secure hashing, and post-quantum cryptography into a single, parallelized hardware architecture optimized for data-intensive and latency-sensitive applications.

The classical cryptographic module supports RSA (4096) and ECC (ECDH/ECDSA over NIST P-192 to P-521) with pipelined modular arithmetic units and accelerated key validation, signature generation, and verification paths. The symmetric core includes a fully unrolled AES engine (supporting AES-128/192/256 with ECB, CBC, CTR, and GCM) for ultra-fast block and streaming encryption. A dedicated SHA-2/HMAC engine supports SHA-224/256/384/512 with high-throughput hash processing and integrated MAC support for secure message authentication.

These engines are hardened against physical attacks using purely algorithmic, RTL-level protections, including power-invariant logic, randomized internal states, and fault detection, which are all implementation-agnostic and portable across back-end flows.

The architecture supports hybrid schemes (e.g., ECDSA + ML-DSA, ECDH + ML-KEM) for smooth migration to quantum-safe protocols. The IP is designed for performance-driven applications such as data centers, secure networking equipment, automotive ECUs, high-end edge computing, and military-grade embedded systems, and supports certification under FIPS 140-3, Common Criteria, and other high-assurance standards.

FortifyIQ’s High-Performance Hybrid Crypto Box IP core delivers exceptional cryptographic performance with long-term quantum resistance and robust physical attack protection, making it the ideal solution for next-generation secure systems that demand speed, scalability, and forward security.

External Dependencies

  • Requires an external cryptographically secure random number generator (CSPRNG)

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-PQC03B – Hybrid Crypto Box IP Core with Classical and Post-Quantum Cryptography for Embedded Systems
  • FIQ-BOX01C – Compact Crypto Box IP Core for Resource-Constrained Devices
  • FIQ-BOX02B – Versatile Crypto Box IP Core with Robust SCA/FI Protections for Balanced Embedded Systems
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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