Contact Us

FIQ-BOX01C Crypto Box Toolset Secure Accelerator

Compact Crypto Box IP Core for Resource-Constrained Devices

FortifyIQ’s Crypto Box IP core is a compact, power-efficient cryptographic engine that combines essential asymmetric algorithms (RSA, ECC) with high-speed AES encryption in a single integrated block. Designed for resource-constrained embedded systems, it enables secure key exchange, digital signatures, and fast data encryption with minimal area and power overhead. Supporting standard modes like ECDH, ECDSA, RSA-2048, and AES-GCM/CTR, the Crypto Box is ideal for secure boot, secure communication, and device authentication. Built-in defenses against side-channel and fault attacks ensure suitability for security certifications such as FIPS 140-3 and Common Criteria.

Features

  • Full Elliptic Curve Support
  • RSA-2048
  • AES-128, AES-192, AES-256
  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s Crypto Box IP core is a compact, integrated cryptographic engine tailored for secure embedded systems with tight area, power, and performance budgets. It combines essential asymmetric cryptographic capabilities (RSA and ECC) with a high-performance AES engine in a unified architecture, delivering robust security for resource-constrained devices such as MCUs, IoT nodes, and sensor hubs. The asymmetric engine supports RSA-2048 and ECC (ECDH/ECDSA over NIST P-192 to P-521), enabling secure key exchange, digital signature verification, and device authentication. The AES engine supports 128-, 192- and 256-bit keys and includes standard modes such as ECB, CBC, CTR, and GCM for secure and authenticated data encryption.

At the core of the Crypto Box is FortifyIQ’s highly innovative and extremely efficient protection of AES against side-channel analysis (SCA) and fault injection (FI) attacks. Protection against SCA is purely algorithmic, implementation-agnostic, and applied at the RTL level, ensuring consistent and portable security across ASIC, SoC, or FPGA implementations regardless of backend flow or technology node.

The IP also supports secure boot and secure firmware update of the Crypto Box itself. Firmware updates are authenticated and validated to ensure only trusted code can be executed, enabling a secure device lifecycle.

FortifyIQ’s Crypto Box IP delivers a compact, self-defending cryptographic foundation for modern embedded platforms, combining classical asymmetric cryptography, efficient symmetric encryption, and lifecycle security—all in a single, low-footprint core optimized for constrained environments.

External Dependencies

  • Requires an external cryptographically secure random number generator (CSPRNG)
  • Requires an external hash function to enable ECDSA operations

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-PQC04B – Accelerator for Classical and Post-Quantum asymmetric cryptography
  • FIQ-BOX02B – Versatile Crypto Box IP Core for Balanced Embedded Systems
  • FIQ-BOX03B – Hybrid Crypto Box IP Core with Classical and PQ Cryptography
View All Products
Get in Touch
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
Request Technical Details