FIQ-AES12T AES-XP-XTS Ultra-High-Performance Secure Core

High-Performance AES-XTS Core with RAMBAM-Based SCA/FI Protection

FortifyIQ’s AES-XTS IP core delivers high-throughput AES-128/256 encryption and decryption in XTS mode, optimized for data-at-rest protection in secure storage systems. Designed with a pipelined architecture, the core achieves low latency and scalable performance for SSDs, encrypted drives, and file systems. It integrates RAMBAM, FortifyIQ’s RTL-level protection scheme that provides strong resistance to side-channel and fault injection attacks through algorithmic countermeasures. Built for systems targeting FIPS 140-3 and Common Criteria, this AES-XTS core ensures robust, efficient, and physically hardened encryption for performance-critical storage applications.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

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Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Payment Systems
  • Secure Communications
  • Network Devices

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Software library 
  • Security documentation

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FIQ-AES13T

Ultra-High-Performance AES-GCM/XTS Core with Integrated SCA/FI Protection

Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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