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Product Overview Certifiable Security IP and Tools

High-assurance cryptographic implementations of AES, HMAC, ECC/RSA, PQC, CryptoBox, and Root-of-Trust families, plus software libraries, all exceptionally efficient (PPA-optimized). Validated across simulation, FPGA, and silicon using FortiEDA, our advanced security evaluation suite, against side-channel and fault-injection attacks. Soft-macro and fully portable, our IP is certification-ready (FIPS 140-3, Common Criteria, EMVCo) and deployable across any technology, foundry, or platform.

Features excellent efficiency with robust protection against side-channel and fault-injection attacks.



Tunable to each deployment’s needs.
Ideal for future-proof security in embedded systems, chips, and chiplets.

Post-Quantum Cryptography Solutions

FIQ-PQC01C
PQC-ML-KEM (Kyber) – Compact
FIQ-PQC02C
PQC-ML-DSA (Dilithium) – Compact
FIQ-PQC03B
ML-KEM & -DSA + support of SPHINCS+, XMSS, LMS – Balanced
FIQ-PQC04B
Hybrid: PQC + Classical RSA/ECC - Balanced
FIQ-PQC05F
Hybrid: PQC + Classical RSA/ECC - Fast
FIQ-PQC01-SW
ML-KEM Hardened Post-Quantum Key Encapsulation SW Library
FIQ-PQC02-SW
ML-DSA Hardened Post-Quantum Signature SW Library
Datasheets available upon request

Delivers exceptional power, performance, and area efficiency while supporting both classical public-key cryptography (RSA, ECC) and post-quantum algorithms (ML-KEM, ML-DSA).

Their flexible architecture unifies key exchange, digital signatures, authenticated encryption, secure boot, and firmware updates, with advanced protections against side-channel and fault injection attacks, providing a secure, future-proof foundation for long life-cycle applications.

Integrated Secure Crypto Subsystems

FIQ-BOX01C
CryptoBox Classical – Compact
FIQ-BOX02B
CryptoBox Classical Plus – Balanced
FIQ-BOX03B
PQ-CryptoBox Hybrid – Balanced
FIQ-BOX04F
PQ-CryptoBox Hybrid – Fast
Datasheets available upon request
Configurable AES IPs for every application, from ULP to pipelined high-throughput. SCA/FIA-resistant. FortiCrypt products utilize protection methods based on finite field arithmetic that implement attack resistance without incurring extra latency costs. Our core protection algorithm was tested rigorously, passing the Test Vector Leakage Assessment (TVLA) test at 1 billion traces, and was validated by a third-party Common Criteria lab. Our cores are fully synthesizable, eliminating the need for custom cells or special place & route handling. They are technology-agnostic, ensuring compatibility and security across diverse platforms and devices. FortiCrypt AES cores deliver high-assurance encryption/decryption with exceptional PPA efficiency, tunable to each deployment case. Their proven protection against side-channel and fault-injection attacks is validated in simulation, FPGA, and in silicon. All cores are designed to support high-assurance certification under standards such as FIPS 140-3 and Common Criteria.

AES IP Cores

AES-SX Family

(Standard, GCM/XTS, DFA-protected)

FIQ-AES01C
AES-SX | ECB-only – Compact
FIQ-AES02B
AES-SX | all modes of operation supported – Balanced
FIQ-AES03F
AES-SX | all modes of operation supported – Fast
FIQ-AES04F
AES-SX-full | encryption + decryption – Fast
FIQ-AES05F
AES-SX-GCM-XTS | pipelined high-throughput – Fast
FIQ-AES06F
AES-SX-GCM-XTS-up | pipelined high-throughput – Fast

AES-STORM Ultra-Low Power (ULP) Family

FIQ-AES07C
AES-SX-ulp-full (STORM) – Compact
FIQ-AES08B
AES-SX-ulp-full (STORM) – Balanced
FIQ-AES09F
AES-SX-ulp-full (STORM) – Fast
FIQ-AES10F
AES-SX-ulp-full-up (STORM) – Fast

AES-XP Turbo Family

(High-throughput, GCM/XTS)

FIQ-AES11T
AES-XP-GCM / encryption + decryption – Turbo
FIQ-AES12T
AES-XP-XTS / encryption + decryption – Turbo
FIQ-AES13T
AES-XP-GCM-XTS / encryption + decryption – Turbo
Datasheets available upon request

Provides high-performance, side-channel and fault injection–resistant hardware implementations of SHA-2 and HMAC. Available in fast-efficient and secure, or highest-security zero-leakage variants, the cores support a range of SHA-2 functions (224, 256, 384, 512) and corresponding HMACs, offering flexibility for embedded and high-assurance systems.



All FortiMAC designs are protected at the RTL-level, and the protection is implementation-agnostic and integration-friendly, supporting systems aiming for the highest levels of Common Criteria and FIPS 140-3 certification.

Hardware IP Cores

Fast-Efficient FortiMAC Family

FIQ-HMAC01F
HMAC-SHA-256 – Fast
FIQ-HMAC02F
HMAC-SHA-512 – Fast

FortiMAC Family

FIQ-HMAC03B
Zero-leakage HMAC-SHA-256 – Balanced
FIQ-HMAC04B
Zero-leakage HMAC-SHA-512 – Balanced
Datasheets available upon request

Delivers high-throughput elliptic curve cryptography (ECC) with advanced protection against side-channel and fault injection attacks. Supporting ECDH, ECDSA, and EdDSA, it combines low-latency performance with efficient power usage for secure, fast SoC integration. The IP is designed to meet the highest levels of FIPS 140-3 and Common Criteria certifications.

Public-Key Accelerators

FIQ-PKA01C
ECC-ECDH-ECDSA – Compact
FIQ-PKA02B
ECC-ECDH-ECDSA – Balanced
FIQ-PKA03B
ECC Curve25519 – Balanced
FIQ-PKA04C
RSA Signature – Compact
Datasheets available upon request

Family of fully customisable Roots of Trust designed for a wide range of applications. All RoTs are hardened against side-channel and fault injection attacks, ensuring strong security even in highly constrained or hostile environments.

The portfolio includes specialized variants for IoT, cloud, chiplets, general-purpose (balanced), and edge AI, providing flexible integration and performance trade-offs to suit your system requirements. FortifyIQ RoTs are fully compatible with Caliptra and support both classical and post-quantum cryptography, enabling robust key management and on-the-fly encryption where applicable. 

Root-of-Trust IP

FIQ-RoT01B
Edge AI – Balanced
FIQ-RoT02F
Data center – Balanced
FIQ-RoT03C
IoT – Compact
FIQ-RoT04B
Chiplet – Balanced
FIQ-RoT00B
General Purpose – Balanced
Datasheets available upon request
MACsec, IPsec, and TLS modules based on our hardened AES-GCM cores. SCA/FIA-resistant.

Cryptographic Protocol Engines

FIQ-PRO01F
MACsec – Fast
FIQ-PRO02F
IPsec – Fast
FIQ-PRO03F
TLS – Fast
Datasheets available upon request

Secure entropy sources for compliant systems.

Number Generators

TRNG
Via partnership
PRNG/DRBG
Datasheets available upon request

Forti Software Libraries SCA/FIA Hardened SW Crypto

FortifyIQ’s software libraries provide devices with certifiable side-channel and fault injection-resistant protection, even in the absence of dedicated security hardware. Each library is optimized for efficient execution, achieving up to ~100 Mbps on 1.2 GHz processors and ~900 Mbps on 3.4 GHz processors, with minimal memory requirements and OTA-readiness. All libraries share a unified API with FortifyIQ hardware IP cores, ensuring consistent integration and enabling seamless migration from software to hardware as system requirements evolve. This interface also supports mixed deployments, where critical operations are accelerated in hardware while others remain in software.

AES Software Library FIQ-AES01-SW

SW library based on the STORM scheme with proven security, validated beyond 100K+ traces

HMAC Software Library
FIQ-HMAC01-SW

SW library based on the threshold Implementation scheme with proven security

ECC/RSA Software Library
FIQ-PK01-SW

Hardened Public Key (ECC, RSA, etc.) cryptography in software library for secure boot, and key exchange

PQC Software Libraries:

Hardened post-quantum cryptography in software for secure boot, key exchange, and digital signature

PQC-ML-KEM-Software Library
FIQ-PQC01-SW

ML-KEM Hardened Post-Quantum Key Encapsulation SW Library

PQC-ML-DSA-Software Library
FIQ-PQC02-SW

ML-DSA Hardened Post-Quantum Signature SW Library

Forti EDA Validation Studios

FortifyIQ offers a unique pre-silicon simulation and analysis solution, Side-Channel Studio, which enables you to eradicate SCA vulnerabilities during the design phase. This can result in significant cost and schedule savings in your product development process. The following tools are included in the Studio.
A simulated oscilloscope that captures traces from the design
A leakage analysis tool that extracts cryptographic keys, using all known attack types on simulated or real traces
Acts as a form of leakage-aware debugging, using Hamming weights and distances
Precisely identifies leakage sources down to specific gates or modules
Collects the data relevant to glitch-related leakage
Identifies glitch-related leakage
Enables trace acquisition in massive numbers in parallel
Fault Injection Studio is a software tool which checks the robustness of your device’s design to FIA and analyzes the results, whether simulated or from an actual device.
Simulates the known types of fault injection
Extracts cryptographic keys by analyzing the results of simulated or real fault injection attacks

Why FortifyIQ ?

Validation Assurance
Both the classical and post-quantum solutions are built on mathematically grounded foundations and deep research and validated with FortiEDA tools at certification-grade levels, using industry-standard TVLA methods on up to 1 billion traces and against real-world SCA/FIA attacks, in simulation, on an FPGA board and where applicable, in silicon and in independent labs.
Comprehensive

Complete suite of crypto solutions: hardware IP, software libraries, subsystems, such as Roots of Trust and CryptoBoxes, plus advanced validation tools.

Certifiable

Designed for all compliance levels, including the highest FIPS 140-3, Common Criteria, SESIP, government and others.

Efficient

Outstanding area, power, and latency even under highest levels of protection.

Deployment-Ready
For any digital device. Soft-macro, easy integration. Ideal for smart cards, automotive, satellites, servers, secure AI, and more. Portable across any implementation, technology, and foundry.

Certifications & Security Validation

FortifyIQ’s AES IP core is SGS Brightsight AVA_VAN.5 validated, representing the highest level of side-channel and fault injection attack resistance in hardware cryptography. All other FortifyIQ products undergo rigorous internal security validation, exceeding the requirements of standards such as FIPS 140-3, SESIP, and similar industry benchmarks. We provide comprehensive security validation documentation to support customer certification efforts and system integration. Our hardware security IPs are engineered to meet the most stringent global security demands, ensuring robust protection without compromising power, performance, or area efficiency.
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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