FortiPQC Hardware Solutions

FortiPQC HW provides a comprehensive suite of post-quantum cryptography hardware, including CryptoBoxes, IP cores, and Root-of-Trust modules. Our CryptoBoxes support both classical and post-quantum algorithms, making them ideal for the migration period when interoperability with existing systems is required.

All solutions implement any of the standardized PQC algorithms aligned with NIST PQC standards, have end-to-end crypto-agility across algorithms, parameters, and protections, and offer certifiable high-assurance resistance to side-channel (SCA) and fault-injection (FIA) attacks.

FortiPQC Hardware IPs

Architecture & Features

  • Fully implementation-, foundry-, and technology-agnostic.
  • Operates standalone or integrated into CryptoBoxes and Roots of Trust (RoTs).
  • Configurable for performance, power, and area targets.
  • Resistant to side-channel and fault injection attacks.
  • Supports FIPS 140-3 up to Level 4, Common Criteria AVA_VAN.5, SESIP up to Level 5 certification targets.
  • System-wide crypto-agility, with algorithms, parameter sets, and protections F/OTA updatable
  • Compatible with FortifyIQ’s unified API, enabling:
Seamless integration with FortiPQC software libraries
OTA updates of post-quantum algorithms without redesigning deployed hardware
Simplified migration from classical to post-quantum cryptography
Flexible combination of hardware and software security layers

Use Cases:
FortiPQC Hardware soft IPs

FortiPQC hardware soft IPs provide post-quantum, SCA/FIA-resistant securitywith exceptional Power-Performance-Area (PPA)and full design portability. They integrate seamlessly into any semiconductor platform, from cost-constrained embedded devices to advanced data-center and multi-chip systems.

General-Purpose and Custom Silicon

Easily integrated into any ASIC, SoC, or FPGA.

Roots of Trust and Secure Elements

Combine PQC with AES, HMAC-SHA2, and RSA/ECC for complete high-assurance cryptography.

Edge, IoT, and Industrial Devices

Compact, low-power configurations maintaining real-time performance.

Cloud, Telecom, and Data Infrastructure

Hardware acceleration for PQ key exchange and signatures at scale.

Defense, Aerospace, and Critical Systems

Optional radiation-tolerant builds for long-term and harsh-environment resilience.

Long-Lifecycle Devices

Future-proof protection ensuring confidentiality and integrity of data over decades.

Ultra-efficient post-quantum hardware IP with built-in, certifiable SCA/FIA protection, optimized per design, supporting all NIST-standardized PQC algorithms with full crypto-agility and seamless integration for hybrid HW/SW deployments.

Hybrid PQC and Classical Crypto (PQ-CryptoBox Hybrid)

FortifyIQ’s CryptoBoxes and Roots of Trust (RoTs) integrate post-quantum (ML-KEM/ML-DSA) and classical cryptography (AES, HMAC, ECC/RSA) in a unified, high-assurance architecture. This hybrid approach allows secure coexistence and gradual migration to post-quantum cryptography while maintaining interoperability with existing infrastructure.

Architecture & Features

  • Combines PQC and classical algorithms in one hardware or mixed hardware & software module
  • Implementation-, foundry-, and technology-agnostic (soft IP cores)
  • Tunable for device- and industry-specific requirements
  • Matches naive PQC hardware implementations in performance and latency
  • End-to-end F/OTAupdatable crypto-agility, includes algorithms, parameter sets, and protections
  • Resistant to side-channel and fault-injection attacks, certifiable to FIPS 140-3 up to Level 4, Common Criteria AVA_VAN.5, SESIP up to Level 5
  • Benefits from the unified API, enabling:
Firmware-OTA (FOTA) updates of PQC algorithms on hybrid modules
Flexibility to combine HW and SW for optimal performance and efficiency
Consistent deployment interface across hardware, software, or hybrid architectures
Future-proof upgrades as new PQC algorithms or countermeasures become available

Use Cases:

  • High-assurance chiplets and SoCs requiring hybrid cryptography support
  • CryptoBoxes and RoTs for cloud, edge, and embedded security
  • Gradual migration from classical to post-quantum cryptography
  • Systems requiring dual-protection for regulatory compliance and high-assurance operations
  • Aerospace and defense applications requiring flexible and radiation-tolerant hybrid cryptography

Ultra-efficient hybrid cryptographic IP cores combining classical and post-quantum algorithms in a single design, with certifiable SCA/FIA protection, optimized per deployment and supporting full crypto-agility across algorithms, parameters, and defenses.

Hybrid: Classical + Post-Quantum Cryptographic Solutions

Datasheets available upon request

Ultra-efficient, high-performance cryptographic IP delivering exceptional power, performance, and area efficiency, unifying classical and post-quantum cryptography in a single design with certifiable SCA/FIA protection, tailored per deployment and enabling full crypto-agility across algorithms, parameters, and protections.  

Integrated Secure Crypto Subsystems

Datasheets available upon request
Datasheets available upon request

Ultra-compact, fully configurable Root of Trust with certifiable SCA/FIA protection, designed for constrained and high-threat environments, Caliptra-compatible and enabling end-to-end crypto-agility for asymmetric cryptography, including PQC, across algorithms, parameters, and protections.

Root-of-Trust IP

FIQ-RoT01B
Edge AI – Balanced
FIQ-RoT02F
Cloud – Fast
FIQ-RoT03C
IoT – Compact
FIQ-RoT04B
Chiplet – Balanced
FIQ-RoT05B
General Purpose – Balanced
Datasheets available upon request
Datasheets available upon request
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own
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