Protecting Quantum Era Cryptography. Today.
FortifyIQ’s IP cores are built with mathematically sound and practically validated patented/patent-pending countermeasures, ensuring resistance to the most advanced physical attacks.
One implementation (RAMBAM) is third-party validated to AVA_VAN.5 level by a leading Common Criteria lab, SGS Brightsight. This design is backed by a peer-reviewed, secure mathematical foundation. (Read more here.)
A second AES variant (STORM) features a formal mathematical proof of its side-channel security, offering high-assurance protection with minimal footprint. (Read the proof here.)
Our HMAC SHA2 uses a patented variant of the TI paradigm, which is proven to offer strong side-channel resistance. (Read the proof.) Our optimized implementation exceeds the highest security compliance standards.
All FortifyIQ IP cores undergo thorough validation to ensure they withstand both passive and active physical attacks. Validation is performed in simulation and on FPGA platforms, with silicon validation conducted where applicable.
Before releasing each of our IPs, our internal team of cryptographers and hardware security experts validates each implementation against all known side-channel attack classes, including:
Differential and Correlation Power Analysis (DPA, CPA), Electromagnetic Analysis (EMA), Timing attacks. In addition, every core is hardened against Fault Injection Attacks (FIA), including voltage, clock, and EM fault injection methods, both detecting (optionally) and preventing where applicable.
For this purpose, FortifyIQ has developed advanced EDA tools for pre-silicon validation. These tools assess TVLA leakage, pinpointing it down to the leaking module, or even gate level, and support validation beyond certification requirements. In addition, they actively attack the RTL design using a full range of side-channel and fault-injection techniques, providing comprehensive security validation. Our tools are applicable to post-silicon verification as well.
After release, and when relevant, our IP cores are validated and/or certified by third party labs either as standalone blocks or integrated in complete secure chips.
FortifyIQ’s hardened countermeasures come with supporting documentation tailored for use in certification processes under SESIP, Common Criteria (up to AVA_VAN.5), FIPS 140-3 (all levels), and relevant industry regulations.
