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Security Validation & Cryptographic Assurance

FortifyIQ’s IP cores are built with mathematically sound and practically validated patented/patent-pending countermeasures, ensuring resistance to the most advanced physical attacks.

AES IP with Proven Resistance

One implementation (RAMBAM) is third-party validated to AVA_VAN.5 level by a leading Common Criteria lab, SGS Brightsight. This design is backed by a peer-reviewed, secure mathematical foundation. (Read more here.)

A second AES variant (STORM) features a formal mathematical proof of its side-channel security, offering high-assurance protection with minimal footprint. (Read the proof here.)

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HMAC-SHA2 Based onThreshold Implementation (TI)

Our HMAC SHA2 uses a patented variant of the TI paradigm, which is proven to offer strong side-channel resistance. (Read the proof.) Our optimized implementation exceeds the highest security compliance standards.

Validation Methodology

All FortifyIQ IP cores undergo thorough validation to ensure they withstand both passive and active physical attacks. Validation is performed in simulation and on FPGA platforms, with silicon validation conducted where applicable.

Before releasing each of our IPs, our internal team of cryptographers and hardware security experts validates each implementation against all known side-channel attack classes, including:

Differential and Correlation Power Analysis (DPA, CPA), Electromagnetic Analysis (EMA), Timing attacks. In addition, every core is hardened against Fault Injection Attacks (FIA), including voltage, clock, and EM fault injection methods, both detecting (optionally) and preventing where applicable.

For this purpose, FortifyIQ has developed advanced EDA tools for pre-silicon validation. These tools assess TVLAleakage, pinpointing it down to the leaking module, or even gate level, and support validation beyond certification requirements. In addition, they actively attack the RTL design using a full range of side-channel and fault-injection techniques, providing comprehensive security validation. Our tools are applicable to post-silicon verification as well.

After release, and when relevant, our IP cores are validated and/or certified by third party labs either as standalone blocks or integrated in complete secure chips.

Designed for Certification and Compliance Support

FortifyIQ’s hardened countermeasures come with supporting documentation tailored for use in certification processes under SESIP, Common Criteria (up to AVA_VAN.5), FIPS 140-3 (all levels), and relevant industry regulations.

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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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