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Digital Identity
& Smart Cards: High Security,
Minimal Footprint

From secure elements and payment cards to e-passports, SIMs, and digital ID tokens, smart cards and digital identity solutions power critical transactions around the world. But their compact, power-constrained environments are especially vulnerable to physical attacks like side-channel analysis (SCA) and fault injection attacks (FIA), putting personal data, credentials, and national assets at risk.

FortifyIQ offers cryptographic solutions designed to meet the toughest security standards in the industry, without compromising on area, latency, or power.

Security Challenges in
Smart Cards and Digital Identity

Digital identity systems and smart cards must meet extreme constraints while maintaining strict compliance with international security standards. Common challenges include:

Constrained Power and Area

Smart cards and ID chips are often based on ultra-compact silicon, where power and die area must be minimized without weakening cryptographic security.

Physical Attack Exposure

Cards and tokens operate in uncontrolled environments, often in the possession of attackers with advanced probing equipment.

Long Lifecycle with No Recall

Once deployed, devices like national ID cards, driver’s licenses, or SIMs must remain secure for 10–15+ years, with no possibility of hardware recall.

Certification Burdens

Regulatory and commercial ecosystems demand certified resistance to SCA/FIA under frameworks like Common Criteria, FIPS 140-3, EMVCo, and GSMA.

Post-Quantum Readiness

Governments and enterprises are planning for post-quantum security. Yet few smart card platforms can afford the overhead of next-generation cryptography.

Why FortifyIQ ?

Smart card and digital identity systems demand maximum protection in minimal silicon area, with long lifecycle, certifiability, and airtight physical security. FortifyIQ delivers high-assurance cryptographic solutions purpose-built for this domain.

  • Symmetric, Asymmetric, and Post-Quantum Crypto
    Our hardware IP and software libraries include AES, HMAC, RSA, ECC, and post-quantum cryptography (ML-KEM/Kyber, ML-DSA/Dilithium), meeting the needs of ICAO 9303, EMV, FIPS 201, and national eID schemes, with options for both secure elements and microcontroller-based implementations.

 

  • Side-Channel & Fault Injection Protection
    Proven resistance to SCA and FIA in hardware and high resistance in software, compliant with all levels of regulatory standards.

 

  • Compact and Energy-Efficient
    Our AES, HMAC, and public key (PKA) IP cores are optimized for minimal gate count and sub-mW power usage, making them ideal for both contact and contactless smart cards,  as well as any embedded secure elements.

 

  • Seamless Integration into Existing Flows
    FortifyIQ cores are synthesizable soft macros (RTL), foundry-agnostic, and compatible with standard interfaces. No custom tooling or instructions needed. Our software libraries require no secure hardware and are deployable in Java Card or RTOS-based systems.

 

  • Roots of Trust for Secure Lifecycle
    We offer compact RoTs for key provisioning, secure boot, and usage-bound cryptographic operations — supporting eID lifecycle management, biometric binding, and secure OTA credentialing.

 

  • Certification-Ready
    FortifyIQ IP is engineered to meet certification standards such as FIPS 140-3 (Level 3/4), Common Criteria EAL4+ and higher with AVA_VAN.5, and SESIP Level 3 and higher, and aligns with market-specific specifications, including EMVCo for payments, GSMA for telecom, and eIDAS, ICAO/MRTD (Doc 9303), ISO/IEC 7816 and 14443 for secure ID documents and smart cards. Deliverables include test vectors and security documentation.

FortifyIQ Provides

Ultra-Compact
Cryptographic IP

Our hardened AES, HMAC, RSA, ECC, etc., and PQC IP cores are designed for low-power, low-area smart card applications,  delivering high performance while withstanding advanced SCA and FIA attacks.

  • ASIC and FPGA ready
  • Side-channel resistance proven in both simulation and silicon

EDA Security Verification Tools

Pre- and post-silicon tools for security validation of smart card chips:

  • Gate-level netlist simulation of SCA/FIA (SideChannel Studio, FaultInjection Studio)
  • Integrates with functional verification workflows, sharing the same testbench.
  • FPGA testing and silicon validation
  • Integrated reporting for certification documentation (e.g., AVA_VAN.5 evidence)

Hardened Software Libraries

For legacy smart cards and cost-sensitive devices that lack secure hardware:

  • Side-channel and fault-injection resistant AES, HMAC, ECC, RSA public key cryptography, and PQC. 
  • AES encryption-only ~4 KB RAM; HMAC ~2 KB RAM
  • Optimized for low-frequency smartcard CPUs and minimal memory footprint
  • OTA upgradable, with formal proofs and testing artifacts
  • Certifiable under Common Criteria, FIPS, and EMVCo

Roots of Trust for Identity & Card OS

FortifyIQ offers a compact and secure Root of Trust IP suitable for identity chips:

  • Personalization, secure boot, and secure updates
  • Compatible with Caliptra, where applicable
  • PQC-enabled variants for digital ID future-proofing

Use Cases:

Digital ID Programs

Secure national eID, ePassport (ICAO-compliant), or digital license deployments with long-term cryptographic resilience

Banking & Payments

Meet EMVCo and PCI security requirements with side-channel protected crypto in hardware or software

Mobile SIM & eSIM

Integrate lightweight cryptography that defends against physical and fault injection threats

Government & Defense Smart Cards

Hardened crypto certified under FIPS 140-3 Level 3/4 and Common Criteria

PKI and Secure Identity Providers

Support strong authentication, key management, and digital signature operations

FortifyIQ: Built for
Secure Identity Systems

With proven cryptographic protections, from tiny secure elements to full-featured ID SoCs, FortifyIQ enables you to build digital identity and smart card systems that meet today’s toughest security standards while being ready for tomorrow’s quantum era.

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Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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