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HOW DO YOU VERIFY THAT YOUR DESIGN IS PROTECTED AGAINST SIDE-CHANNEL AND FAULT INJECTION ATTACKS?

Without FortifyIQ’s tools, today’s state of the verification process is costly, tedious, and can take several months. How can you perform security verification in a reasonable amount of time and for a reasonable cost? This is precisely what FortifyIQ makes possible by closing the gap, allowing you to verify the security in the pre-silicon stage—in the same way the functionality is verified. In other words, FortifyIQ revolutionizes the process, accelerating your entire cycle. This video shows how the virtual capabilities offered will run your security verification while you circumvent physical verification labs.

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Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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