FortifyIQ’s AES-SW library delivers high-performance protection against side-channel (SCA) and fault injection attacks (FIA) through OTA deployment, enabling compliance with FIPS 140-3, Common Criteria AVA_VAN.5, and SESIP.
It secures both new and already-deployed devices, including those without hardware countermeasures, and is proven in millions of systems.
AES-SW achieves outstanding performance even on low-end processors, 100 Mbps on a 1.2 GHz ARM and 900 Mbps on a 3.4 GHz laptop, while supporting all AES chaining modes. The library integrates STORM, FortifyIQ’s advanced protection scheme, to block DPA, SIFA, cache, and other advanced attacks.
Portable and processor-agnostic, AES-SW provides consistent, high-assurance security across MPUs and MCUs. Validation includes no TVLA leakage in 100K noiseless traces and proven resistance at Common Criteria AVA_VAN.5 and FIPS 140-3 Levels 3–4.
A command-line interface is included for rapid encryption and decryption tasks.
Tech Specs
Performance note:
FortifyIQ software libraries provide robust security and full cryptographic functionality for many applications. However, systems with extreme performance or low-latency requirements may benefit from hardware-based protection.
DPA- and FIA-Resistant Ultra High Bandwidth FortiCrypt AES IP Core
DPA- and FIA-Resistant Ultra Low Power FortiCrypt AES IP Core
DPA- and FIA-Resistant Ultra Compact FortiCrypt AES IP Core
DPA- and FIA-Resistant Balanced FortiCrypt AES IP Core
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”
