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FIQ-PQC05F High-Performance Hybrid Classical and Post-Quantum Cryptography

Hybrid Classical and Post-Quantum Cryptography IP Core for Future-Proof Security

FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) algorithms in a unified architecture optimized for maximum throughput. Designed for security-critical systems requiring long-term protection and cryptographic agility, the IP enables hybrid key exchange and digital signature schemes aligned with NIST recommendations. Featuring parallelized arithmetic units, pipelined execution, and shared hash acceleration, it offers exceptional performance without compromising security. With built-in SCA/FIA protections and support for FIPS 140-3 and Common Criteria certification, this core is ideal for next-generation secure boot, firmware authentication, and high-speed communication protocols.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • Automotive Systems
  • Embedded and Industrial Control
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s High-Performance Hybrid Cryptography IP core is a scalable, integrated hardware accelerator that supports both classical and post-quantum cryptographic algorithms, optimized for maximum throughput and minimal latency in demanding security applications. It enables hybrid cryptographic schemes by combining RSA (2048/4096), ECC (ECDH/ECDSA over NIST P-192 to P-521), ML-KEM (Kyber), and ML-DSA (Dilithium) within a unified, performance-oriented architecture.

The IP features parallel execution units tailored for each cryptographic domain: a high-speed modular arithmetic engine for RSA and ECC, an optimized Number-Theoretic Transform (NTT) engine for lattice-based PQC, and pipelined SHA-2/SHA-3 hash accelerators shared across algorithms. These units are tightly integrated to support hybrid operations such as ECDSA + Dilithium signature verification or ECDH + ML-KEM key agreement with minimal overhead.

Although high performance is the primary focus, the IP also includes robust countermeasures against side-channel and fault injection attacks, making it suitable for deployment in environments requiring FIPS 140-3 or Common Criteria certification.

FortifyIQ’s High-Performance Hybrid Cryptography IP enables next-generation systems to achieve quantum-resilient security at wire-speed, without compromising interoperability, certification readiness, or long-term cryptographic agility.

External Dependencies

  • Requires an external cryptographically secure random number generator (CSPRNG)

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-BOX04F – Cryptographic tools set including PQC support
  • FIQ-PQC03B – Versatile PQC balanced accelerator
  • FIQ-PQC04B – Balanced accelerator for Classical and Post-Quantum asymmetric cryptography
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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