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FIQ-PQC03B Post-Quantum Accelerator

Versatile Post-Quantum Cryptography IP Core for Balanced Performance, Area, and Power

FortifyIQ’s Post-Quantum Cryptography IP core provides a high-efficiency hardware solution supporting ML-KEM (Kyber) and ML-DSA (Dilithium) as standardized in FIPS 203 and 204, along with additional hash-based signature schemes including SPHINCS+, XMSS, and LMS. Designed for systems requiring a balanced trade-off between performance, area, and power, the IP delivers robust, quantum-safe key exchange and digital signature capabilities. Its scalable architecture supports integration into a wide range of SoCs, with built-in protections against side-channel and fault injection attacks to enable certification under FIPS 140-3 and Common Criteria. Flexible interfaces and modular design ensure seamless adoption in future-ready, security-critical applications.

Features

  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices
Technical Overview

FortifyIQ’s Post-Quantum Cryptography IP is a flexible, high-efficiency hardware core supporting a wide portfolio of NIST-approved and standardized quantum-resistant algorithms, including ML-KEM (Kyber) for key encapsulation, ML-DSA (Dilithium) for digital signatures, and optional support for hash-based signature schemes such as SPHINCS+, XMSS, and LMS. Designed for systems with balanced performance, power, and area constraints, the IP is ideal for secure SoC integration in next-generation embedded platforms.

The architecture includes optimized engines for Number-Theoretic Transform (NTT) and modular arithmetic, supporting all defined security levels of ML-KEM and ML-DSA. For hash-based signature schemes, the IP leverages configurable hash acceleration and stateful signature logic to support SPHINCS+ (stateless), XMSS, and LMS (stateful) with minimal software overhead. This enables developers to select the appropriate post-quantum signature scheme based on lifecycle, certification, or application requirements.

To support secure deployment in high-assurance environments, the IP includes configurable countermeasures against side-channel and fault injection attacks. These protections help ensure the design is certifiable under FIPS 140-3 and Common Criteria. FortifyIQ’s Post-Quantum IP is enabling SoC designers to adopt quantum-safe cryptography without compromising on efficiency, scalability, or security.

External Dependencies

  • Requires an external cryptographically secure random number generator (CSPRNG)

Deliverables

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Related Products

  • FIQ-BOX03B – Cryptographic tools set including PQC support
  • FIQ-PQC02C – PQC DSA Dilithium compact accelerator
  • FIQ-PQC01C – PQC KEM Kaliber compact accelerator
  • FIQ-PQC04B – Accelerator for Classical and Post-Quantum asymmetric cryptography
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FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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