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THE HARDWARE SECURITY DILEMMA

Mitigate the risk and protect your hardware against side-channel attacks on its secure element.

Hardware design needs to be protected from side-channel attacks in order to make the product secure. In order to test a product’s security, it naturally needs to be manufactured first. That progression from hardware design to a testable final product can take months and cost millions of dollars. If a design flaw is discovered upon testing, delays and rework on a massive scale result in material consequences for the timing and cost of the product launch.

All OEMs and microchip manufacturers face this dilemma.

How will you solve it in your next innovation cycle?

Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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