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FORTIFYIQ PROTECTED IP INTRODUCTION

FortifyIQ has made it possible to assess and increase resistance to side-channel attacks at the pre-silicon stage. In this video, you will get a better understanding of the various tools developed for pre-silicon verification and the many professional services offered by FortifyIQ. Explore FortifyIQ’s range of protected ultra-high bandwidth AES XTS and GCM engines, as well as the protected AES IP core that’s used as the building block for the protected IP engines. Learn about the various core configurations, from cost and power-efficient cores for IoT (starting at 25K gates) to ultra-high bandwidth multiple-pipeline cores for data centers (128 Gbps per pipeline @1 GHz).

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FORTIFYIQ PROTECTED IP INTRODUCTION

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Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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