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FortiEDA/
Fault Injection Studio

Pre-Silicon Security Validation Against Fault Injection Attacks

Overview

FortifyIQ’s Fault Injection Studio enables engineers to evaluate and strengthen hardware designs against fault injection attacks, e.g., DFA, SIFA, and AFA. By simulating faults at the algorithmic and gate levels, the studio validates countermeasure effectiveness before tapeout and supports FPGA and post-silicon validation.

Key Benefits

Early Detection of Vulnerability 
to Fault-Injection Attacks:

Identify vulnerabilities in RTL, gate-level, or post-layout designs.


Evaluation of the Rate 
of Effective Faults:

Assesses the quality of the error correction.

Assessment of the Quality 
of Error Detection:

Acquire and process traces in parallel at exceptional speed and scale.

Countermeasure Validation:

Test mitigation strategies under realistic fault scenarios.

Extensible Architecture:

Plugin-based system for new or proprietary fault injection attacks and models.

Seamless Integration:

Works within standard verification flows via DPI.

Certification Support:

Prepares designs for FIPS 140-3, Common Criteria, and SESIP evaluation.


Tools in Fault Injection Studio

FI Simulator

Simulates fault injection attacks, e.g. DFA, SIFA, and AFA, across design stages

Countermeasure Validator

Verifies the effectiveness of structural or algorithmic protections

Plugin Manager

Incorporates user-defined or proprietary fault models

Analyzer Engine

Generates reports, metrics

Primary Use Cases

Validation of cryptographic IP under fault injection attacks
Verification of countermeasures in new or modified designs
Pre-certification evaluation for FIPS, CC, or SESIP
Post-silicon analysis of real fault injection results
Research and prototyping of advanced fault models and mitigations
Assessment of the quality of error detection

Technical Highlights

Capability

Description

Integration

Integrates with functional verification workflows via DPI.

Extensibility

Supports plugin-based custom fault models.

Analyzer Engines

Evaluates DFA, SIFA, and AFA, producing detailed reports.

Simulation Support

RTL, gate-level, post-layout, FPGA and silicon-compatible.

Automation & APIs

Auto-generates testbenches and Makefiles; CLI and Python API.

Read Whitepaper
Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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