Contact Us

FortiEDA Security Assessment Tools

Comprehensive Pre- and Post-Silicon Security Validation Against Side-Channel and Fault Injection Attacks

Overview

FortiEDA is FortifyIQ’s suite of Electronic Design Automation (EDA) tools for evaluating hardware resistance against Side-Channel (SCA) and Fault Injection Attacks (FIA). It enables hardware designers and validation engineers to detect, locate, and mitigate vulnerabilities from the earliest RTL stage through GDSII and perform post-silicon security validation. FortiEDA integrates directly into standard verification flows through the DPI interface, automatically generating modified testbenches and build scripts. Security assessments run alongside functional verification with minimal setup.

Product Studios

Analyzes leakage vulnerabilities throughout the design flow by generating simulated power traces, performing statistical leakage tests (Welch’s t-test / TVLA), and applying advanced side-channel attack engines (DPA, CPA, template, and deep learning). Key advantages include a proprietary parallel trace engine that enables high-speed acquisition and analysis of up to billions of traces without storage bottlenecks. Precise leakage pinpointing isolates vulnerable modules, signals, or gates. Supports evaluation in simulation, FPGA prototypes, and post-silicon measurements.
See more
Read Whitepaper

Evaluates and strengthens designs against DFA, SIFA, and AFA by simulating fault scenarios at the algorithmic level and validating countermeasure effectiveness before tapeout. A plugin-based architecture supports new or proprietary attack models for rapid adaptation.

See more
Read Whitepaper

Key Benefits

Early Vulnerability Detection:

Identify leakage or fault issues at RTL, gate, or post-layout stages.

End-to-End Security Coverage:

Assess from RTL to post-silicon using a single framework.

High-Throughput Analysis:

Acquire and process traces in parallel at exceptional speed and scale.

Seamless Integration:

Works with all major SystemVerilog simulators via DPI; auto-generates testbenches and Makefiles.

Accelerated Certification Readiness:

Validate compliance with FIPS 140-3, Common Criteria, and SESIP before submission.

Technical Highlights

Capability

Description

Integration

Interfaces with functional verification workflows using DPI.

Parallel Trace Engine

Multi-threaded architecture captures and processes up to billions of traces concurrently without I/O or storage limits.

Leakage Pinpointing

Identifies specific modules, signals, or gates responsible for leakage.

Analyzer Engines

Includes Welch’s t-test (TVLA), CPA, template, deep learning, DFA, SIFA, and AFA analyses.

Simulation Support

Operates from RTL through gate-level and post-layout; supports FPGA and silicon traces.

Automation & APIs

Auto-generates testbenches and Makefiles; includes CLI and Python API for scripting and CI/CD integration.

Trace & Fault Formats

Exports in standard formats (.npy, .trc, .trs) for interoperability.

Plugin Extensibility

Supports user-defined attack and analysis plugins.

Primary Use Cases

Security verification of cryptographic IPs (AES, SHA2, RSA, EdDSA, PQC, etc.)
Validation of algorithmic and structural countermeasures against SCA/FIA
Pre-certification security assessment prior to FIPS, CC, or SESIP submission
Post-silicon analysis of measured traces and fault data
Research and development of new attack models or protections

Experience the power and simplicity of our solution in action

About FortifyIQ

FortifyIQ engineers certifiable cryptographic IP cores, software libraries, and roots of trust with traditional and post-quantum algorithms, all hardened against side-channel and fault injection attacks, without compromising performance, area, or energy efficiency. Our solutions are foundry- and platform-agnostic, integrating securely across a wide spectrum, from smart cards and IoT devices to AI accelerators and cloud systems.

Backed by a strong portfolio of granted and pending patents, research, and formal and practical security proofs, FortifyIQ’s IP is developed and validated using our own pre- and post-silicon EDA tools, enabling systematic evaluation of physical attack resilience.

FortifyIQ delivers advanced cryptography that is certifiable, reliable, and built to meet the challenges of high-assurance, real-world applications.

FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
Request Technical Details