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Side-Channel Studio

Side-channel attacks are a pervasive threat to hardware security, particularly in cryptographic systems where they can leak sensitive information. While some leakage can be mitigated through simple countermeasures, advanced attacks require detailed analysis and design-level protections. FortifyIQ’s Side-Channel Studio provides a comprehensive EDA solution for evaluating and strengthening hardware against side-channel attacks. Engineers can validate designs in pre-silicon simulation, on FPGA boards, and post-silicon, gaining the insight and confidence needed to meet certification requirements and ensure robust protection.

Fault Injection Studio

Fault Injection Attacks pose a growing threat to the security of hardware systems, particularly in cryptographic contexts where they can lead to full key recovery. While simple FIAs can often be mitigated through detection
mechanisms, cryptographic FIAs — especially ineffective fault attacks — require deeper, design-level
countermeasures. FortifyIQ’s Fault Injection Studio addresses this challenge with a comprehensive EDA solution for evaluating and improving algorithmic protections against fault injection attacks.

THE HARDWARE SECURITY DILEMMA

FortifyIQ offers a complete suite of solutions for DPA, SPA and FI detection, analysis, and recommendations for protecting your microchips and products from successful DPA and FI attacks.

Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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