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FORTIFYIQ PRODUCTS AND TECHNOLOGY OVERVIEW

FORTIFYIQ PRODUCTS AND TECHNOLOGY OVERVIEW Unlike software security, hardware security cannot be added to an existing chip. Therefore, it is essential to plan and implement defenses against side-channel and fault injection attacks before a chip is manufactured. You need the help of a highly qualified specialist to design defenses against such attacks. The question is […]

HARDWARE SECURITY ATTACKS – A CLEAR AND PRESENT DANGER

HARDWARE SECURITY ATTACKS – A CLEAR AND PRESENT DANGER There is a lot of secret data around us. The most valuable secrets such as cryptographic keys should be given the best possible protections. The key to doing that is burying the data in hardware. Though nowadays, you need more than just that to secure your […]

HOW FAST IS THE FORTIFYIQ HARDWARE VERIFICATION SOLUTION?

HOW FAST IS THE FORTIFYIQ HARDWARE VERIFICATION SOLUTION? How fast can you create traces using ScopeIQ? Watch this video and learn how to focus on specific portions of your design and target the simulation on the security algorithm—to increase productivity and dramatically improve the simulation turnaround time. You’ll also learn about how SideChannel Studio can […]

WHAT ARE THE DATA REQUIREMENTS FOR FAULTINJECTION STUDIO?

WHAT ARE THE DATA REQUIREMENTS FOR FAULTINJECTION STUDIO? Active FortifyIQ customers receive updates to the library of attack plugins, and they also have the ability to add their own pairs of attack plugins written in C++ or Python. If they want to use FaultInjection Studio for a specific attack, all they need to really do […]

WHAT ARE THE DATA REQUIREMENTS FOR SIDECHANNEL STUDIO?

WHAT ARE THE DATA REQUIREMENTS FOR SIDECHANNEL STUDIO? The ScopeIQ simulator of SideChannel studio receives 3 major inputs: the gate level netlist, the target cell library, and a test bench. Side-channel traces produced by ScopeIQrunning are fed to the side-channel trace analyzer called ScoreIQ. Customers can then choose which plugin attack module ScoreIQshould run. Depending […]

FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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