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Semiconductor IP Security &
Anti-Cloning

Protect Your Silicon IP From Foundry to Field

Modern SoCs and silicon IP blocks are increasingly at risk of unauthorized replication, reverse engineering, and cryptographic key leakage, especially as chips move through globalized and opaque supply chains. FortifyIQ offers certifiable, physically hardened cryptographic IP and software designed to prevent cloning, enforce licensing, and validate chip authenticity at every stage from tape-out to end use.

Your Semiconductor Security Challenges

Protecting IP in silicon involves a unique set of risks, particularly when working with external fabs or selling soft IP to downstream integrators:

Clone-Proof IP Distribution

Preventing reuse, extraction, or tampering of high-value soft or hard IP blocks across uncontrolled supply chains.

Tamper-Resistant Licensing & Activation

Enforcing usage limitations through cryptographic licensing tied to chip-specific secrets.

Foundry-Independent Assurance

Ensuring consistent security regardless of process technology, foundry, or silicon platform.

Lifecycle-Critical Root of Trust

Secure boot and attestation must be embedded early, with no impact on PPA or certification.

Pre- and Post-Silicon Security Validation

Vulnerabilities must be detected before tape-out and confirmed after fabrication.

Why FortifyIQ ?

FortifyIQ offers hardened cryptographic solutions purpose-built for silicon IP protection, licensing enforcement, and clone detection validated through the world’s highest security standards.

  • Physically Hardened Crypto IPs & Libraries AES, HMAC, ECC/RSA, and PQC implementations resistant to side-channel and fault injection attacks, validated and certifiable under FIPS 140-3 Level 3/4, SESIP Level 3+, and Common Criteria AVA_VAN.5.
  • Technology-, Implementation-, and Foundry-Agnostic FortifyIQ’s cryptographic protection is algorithmic and soft macro-based, seamlessly integrated into any design, regardless of node, foundry, or toolchain. Ideal for soft IP vendors, SoC integrators, and platform makers alike.
  • Anti-Cloning & Licensing Enforcement Hardware IP Cryptobox IPs combining AES, HMAC, ECC/RSA, and PQC, offering secure key storage, licensing control, and tamper detection in a low-area, high-performance package.
  • Trusted Roots of Trust for IP and SoCs Secure boot, lifecycle enforcement, and runtime crypto in a drop-in root of trust, built to work with Caliptra and OpenTitan. FortifyIQ enhancements include SCA/FIA resistance and certifiability with best-in-class power, performance, and area (PPA).
  • Software Libraries for Legacy or Hardware-Limited Platforms Hardened AES, HMAC, and public key libraries with proven SCA/FIA resistance, field-deployable without hardware changes. Supports secure provisioning, firmware validation, and OTA-enforced licensing. Designed to protect cryptographic assets and IP in legacy or clone-prone environments. PQC coming soon.
  • EDA Tools for Security Validation Before Tapeout Side Channel Studio and Fault Injection Studio identify vulnerabilities at RTL and gate level. Validate AVA_VAN.5 level resistance pre-silicon and confirm protection post-silicon.
  • Certification Support All IPs are supported with documentation aligned to FIPS 140-3, Common Criteria, SESIP, and other relevant frameworks. Our team can assist with validation strategy, documentation, and third-party lab coordination.

FortifyIQ Security Solutions for Semiconductor IP

Hardened Crypto IP & Software Libraries

  • AES, HMAC, PKA (ECC/RSA), PQC (coming soon), protected against SCA and FIA
  • Certifiable under FIPS 140-3, SESIP, Common Criteria AVA_VAN.5
  • Soft macro implementation, no silicon-specific constraints
  • Drop-in CryptoBox IPs or standalone cores

Anti-Cloning & Licensing IP

  • Secure subsystem integrating all key cryptographic operations
  • Enforces licensing, supports key storage and revocation, and detects tampering
  • Compact, low-latency, and soft macro-based for integration flexibility

Software Crypto for Field Enforcement

  • AES-256, HMAC-SHA2, ECC/RSA in hardened software
  • OTA-updatable enforcement of IP licensing or provisioning
  • Ideal for prototyping, constrained systems, or in-field activation
  • PQC software (ML-KEM, ML-DSA) coming soon

Secure Root-of-Trust IPs

  • Secure boot, attestation, lifecycle management
  • Compatible with Caliptra; enhanced for FIA/SCA resistance with excellent power, performance, and area
  • On-the-fly encryption/decryption available for chiplets, and flash memory protection
  • Full documentation and support for certification

Use Cases:
Silicon IP Protection Across the Lifecycle

Secure IP Licensing

Prevent cloning and unauthorized use of IP cores with embedded licensing keys

Secure Provisioning & Boot-Time Decryption

RoTs with hardened AES enable safe chip startup and configuration

Clone Detection & Device-Specific Attestation

Use unique secrets for hardware-based authenticity

Pre-Tapeout Vulnerability Assessment

Detect issues early using FortifyIQ’s EDA tools with AVA_VAN.5 level coverage

Compliance & Certification Support

Cryptographic modules validated to FIPS 140-3 Levels 3 and 4, SESIP Level 3 and higher, and Common Criteria AVA_VAN.5
Documentation for certification-ready IP

RoT integration, secure licensing, and key lifecycle security

Mapped Standards and Frameworks FIPS 140-3 | Common Criteria AVA_VAN.5 | SESIP | ISO 26262 (as applicable)
Security Validation & Cryptographic Assurance

Secure the Core of Your Silicon Value

FortifyIQ protects what matters most in semiconductors: your IP. Whether you license blocks to third parties or build complete SoCs, we help ensure your cryptography is tamper-resistant, clone-proof, and ready for compliance from RTL to runtime.

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Experts
Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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