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FortifyIQ is the Finalist for the Milipol Paris Innovation Awards, Cybersecurity and Smart & Safe Cities Categories

October 29, 2019

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Comprehensive Side-Channel Attack Solution Suite to Demo at Milipol Paris 2019

At Milipol Paris 2019, FortifyIQ has been selected to be one of the top three finalists of the Milipol Innovation Award in two categories: “Cybersecurity” and “Smart and Safe Cities.”

Alexander Kesler, FortifyIQ co-founder and CEO, is surprised and humbled: “We are very much honored to be nominated as a finalist in two Milipol Innovation Awards categories, among some of the finest innovators in this field”.

“Our solutions solve the urgent need for chip manufacturers to fortify chips against attacks in the most comprehensive way possible,” said Mr. Kesler. “As the leading event dedicated to critical infrastructure security and safety, Milipol Paris 2019 is the ideal venue for demonstrating FortifyIQ’s unique and game-changing technological capabilities to the world that’s been trying to solve this problem for quite some time,” added Mr. Kesler.

At the event, Yuri Kreimer, FortifyIQ CTO, will complete a full cycle power analysis of hardware, demonstrating how easy it is to break into a device by analyzing power consumption patterns produced by the chip. We are going to show the weakness of the hardware chip and how it can be used to take control over hardware.

FortifyIQ will be exhibiting at Milipol Paris 2019 on November 19-22. Trade show attendees, media, and any critical infrastructure owners interested in comprehensive side-channel attack protection can stop by the booth # 4 S 015 located in Startup Zone, Hall 4.

FortifyIQ AVA_VAN.5
Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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