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FortifyIQ News for SideChannel Studio, the pre-silicon simulation and analysis solution.

May 20, 2021

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“We recently expanded the functionality so that external simulators are supported via the Verilog Procedural Interface (VPI) interface.
This enables integration with industry-standard functional simulators.”

Side Channel Attacks (SCA) extract cryptographic keys from hardware systems by analyzing power traces or electromagnetic emission data from the target device along with plain and/or cipher data. The traditional approach to deal with SCA of measuring device parameters after manufacturing is expensive and time-consuming.

How do you design security INTO your designs as early in the development process as possible?
Let FortifyIQ help you with SideChannel Studio.

The simulation engine portion of SideChannel Studio, SCOPE IQ, a “virtual oscilloscope probe”, uses an exclusive, patent-pending method of accurately simulating side channel leakages, which threaten the security perimeter of the designed chip. SCOPE IQ has extremely high performance which is further boosted by distributed processing.

The SCA data analyzer, SCORE IQ – “Side Channel Output Results Evaluator”, receives traces, simulated at the pre-silicon stage from SCORE IQ or measured at the post silicon stage, and automatically extracts cryptographic keys from the traces if the design is vulnerable to SCA.

Are your designs vulnerable? Let FortifyIQ help you with SideChannel Studio!

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Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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