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IP Catalog

FortifyIQ offers a new generation of products, protected against SCA and FIA, which utilize proven, purely algorithmic, implementation-agnostic algorithms and deliver performance at least as fast as conventional unprotected versions.

Configurable AES IPs for every application, from ULP to pipelined high-throughput.
SCA/FIA-resistant MAC cores with performance and protection options.
Secure Asymmetric (ECC, RSA, etc.) cores with modular multipliers and Curve25519 support.
All-in-one secure crypto blocks with boot/update support, ready for chiplet and SoC integration, with extraordinary PPA.
MACsec, IPsec, and TLS modules based on our hardened AES-GCM cores.
Transition-ready cryptographic cores for a hybrid and post-quantum world.
Secure entropy sources for compliant systems.
Flexible, high-efficiency RoT solutions across markets.
FortifyIQ’s Cryptographic Libraries bring high-assurance security to devices that can’t rely on hardware protection, whether due to cost constraints or field deployment.

FortifyIQ develops HW security IP cores fortified against Side-Channel (SCA) and Fault Injection attacks (FIA), while preserving the original AES goals of speed, low latency, and low power usage. We also offer high-performance software libraries and EDA tools for pre- and post-silicon security assessment.

FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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