FortiPQC Hardware IPs

FortiPQC Hardware soft IPs deliver post-quantum cryptography with certifiable resistance to side-channel and fault-injection attacks (SCA/FIA). Implementing ML-KEM and ML-DSA aligned with NIST PQC standards, these cores provide extraordinary PPA, and field-proven physical security.

Architecture & Features

  • Fully implementation-, foundry-, and technology-agnostic.
  • Operates standalone or integrated into CryptoBoxes and Roots of Trust (RoTs).
  • Configurable for performance, power, and area targets.
  • Resistant to side-channel and fault injection attacks.
  • Supports FIPS 140-3 up to Level 4, Common Criteria AVA_VAN.5, SESIP up to Level 5 certification targets.
  • Compatible with FortifyIQ’s unified API, enabling:
Seamless integration with FortiPQC software libraries
OTA updates of post-quantum algorithms without redesigning deployed hardware
Simplified migration from classical to post-quantum cryptography
Flexible combination of hardware and software security layers

Use Cases:
FortiPQC Hardware soft IPs

FortiPQC hardware soft IPs provide post-quantum, SCA/FIA-resistant security with exceptional Power-Performance-Area (PPA) and full design portability. They integrate seamlessly into any semiconductor platform, from cost-constrained embedded devices to advanced data-center and multi-chip systems.

General-Purpose and Custom Silicon

Easily integrated into any ASIC, SoC, or FPGA.

Roots of Trust and Secure Elements

Combine PQC with AES, HMAC-SHA2, and RSA/ECC for complete high-assurance cryptography.

Edge, IoT, and Industrial Devices

Compact, low-power configurations maintaining real-time performance.

Cloud, Telecom, and Data Infrastructure

Hardware acceleration for PQ key exchange and signatures at scale.

Defense, Aerospace, and Critical Systems

Optional radiation-tolerant builds for long-term and harsh-environment resilience.

Long-Lifecycle Devices

Future-proof protection ensuring confidentiality and integrity of data over decades.

Features excellent PPA efficiency with robust protection against side-channel and fault-injection attacks.



Tunable to each deployment’s needs.
Ideal for future-proof security in embedded systems, chips, and chiplets.

Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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