Explanatory Videos

Our explanatory videos break down complex hardware security concepts into clear, visual stories. They showcase how FortifyIQ’s technologies detect and prevent side-channel and fault-injection attacks, strengthen cryptographic modules, and enhance overall device resilience. 

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Here we present RAMBAM, our patented novel concept of designing countermeasures against side-channel attacks and SIFA on AES using redundant representations of finite field elements. It enables trade-offs between gate count, maximal frequency, performance, level of robustness to first and higher-order side-channel attacks and SIFA-1. We present an analytical model that explains the leakage reduction, and a leakage assessment using TVLA methodology on an FPGA board, showing resilience to at least 348M traces with 16 Sboxes.
We present Carry-based Differential Power Analysis (CDPA) — a new side-channel attack targeting algorithms that use arithmetic addition. Applied to HMAC-SHA-2, CDPA enables full key recovery from power traces, both in simulation and on FPGA hardware. With as few as 30K traces, secret keys can be recovered in some cases, allowing for forging the HMAC-SHA-2 signature of any message, and with 275K traces, the success rate reaches 100%. This demonstrates that even pure hardware implementations of HMAC-SHA-2 are vulnerable unless properly protected. To our knowledge, this is the first successful non-profiling attack on hardware HMAC-SHA-2.
Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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