Academic Papers

This section features FortifyIQ’s academic publications. Some papers present AES protection techniques against side-channel and fault injection attacks with minimal area, power, and performance overhead, while others demonstrate side-channel attacks on SHA-2-based HMAC, highlighting the need for robust countermeasures.

Most Recent

STORM effectively solves the long-standing challenge of combining high security against SCA with low gate count and high performance for AES implementations by offering a different tradeoff (memory utilization) that may be preferable to RAMBAM in many practical cases.
In this paper, FortifyIQ introduces Carry-based Differential Power Analysis (CDPA), a novel methodology that allows for attacking schemes involving arithmetical addition. This methodology is applied to what is believed to be the first published full-fledged attack on HMAC-SHA-2 which does not require a profiling stage.
FortifyIQ presents a novel practical template attack on HMAC-SHA-2 intended primarily against its implementations in hardware. Side-channel attacks pose a threat to cryptographic algorithms. HMAC is an important use case of a hash function, in which the input is partially secret and thus unknown to the attacker. Despite a few publications that discuss applications of power analysis techniques to attack HMAC-SHA-2, this is the first generic method that shows a full attack on its hardware implementation.
This is an academic paper describing a protection method for AES which is very efficient, and configurable for any application. It introduces RAMBAM, an innovative algebraic masking technique designed to protect against side-channel attacks and SIFA1. 
Fortify’s AES security evaluation by SGS

“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”

” The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own.”

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