Design side-channel vulnerability out of your hardware before you build it.

Differential Power Analysis (DPA) and Fault Injection attacks extract cryptographic keys from a hardware system by analyzing power traces from the target device along with the corresponding collection of plain and cipher data. The best way to defeat these and other side-channel attacks is by means of a pre-silicon simulation that would enable you to eradicate vulnerabilities during the design phase.

That’s the benefit of FortifyIQ’s power consumption simulator, PowerIQ. It is a software tool that simulates power consumption traces from a cryptographic hardware device based on a standard textual representation of the device’s circuitry. It is much faster and less expensive to use PowerIQ in pre-silicon stage than using an oscilloscope to obtain power consumption traces from the actual physical device after it is built.

"FortifyIQ's software has the potential to dramatically reduce the cost and delay associated with the manufacturing of DPA-protected devices..." Adi Shamir, the ‘S’ in RSA and Turing prize winner who evaluated our mathematical model as well as the FortifyIQ software.

You could potentially save — in tapeout, masks, and fab run — millions of dollars and several months in your product development process.

Our innovation is a novel, patent-pending method of accurately simulating the power consumption of the designed chip. PowerIQ uses information usually available at the start of the hardware development and can be used at any phase of the hardware development cycle – RTL, post-synthesis (gate-level NetList), as well as post “place-and-route.” While we find that the most effective stage is the post syntheses (gate-level Netlist) stage, the results of the gate-level Netlist-based trace analyses can still be formulated in terms of RTL and solved at the RTL level.

PowerIQ Highlights:

The use of software rather than a hardware test setup eliminates noise (unavoidable with physical measurements), thereby improving accuracy and reducing sample volumes.

Modeling only a portion of the design at a time (for example, new IP blocks in a design upgrade) can greatly reduce the volume of data that must be processed, analyzed, and reviewed all at once.

Enabling partial analysis for every module and every type of gate means that you can easily localize the sources of power leaks to any segment of the design in order to take remediation steps faster.

PowerIQ modeling enables “what if” analyses that can help find optimal solutions for design errors faster.

One of the most painful leaks is a “glitch” — the volatility of electrical current before it stabilizes at a clock boundary. PowerIQ can simulate DPA glitch vulnerability, which traditional power consumption techniques can’t see.
Sometimes a DPA attack defines its own method (strategy) on how to generate the test data (plain text). To see if you are vulnerable to such an attack, PowerIQ includes a tool that can output test samples consistent with any foreseeable DPA attack strategy.

Traces are formatted in the de facto oscilloscope standard (LeCroy) for easy input to any analytical tool.

PowerIQ offers verification to ensure that the design being tested is fault injection resistant.

Simulations are distributable and can run across all available CPUs.

For many attacks, only the information about power consumption during specific clocks needs to be collected.