Differential Power Analysis (DPA) and Fault Injection attacks extract cryptographic keys from a hardware system by analyzing power traces from the target device along with the corresponding collection of plain and cipher data. The best way to defeat these and other side-channel attacks is by means of a pre-silicon simulation that would enable you to eradicate vulnerabilities during the design phase.
That’s the benefit of FortifyIQ’s power consumption simulator, PowerIQ. It is a software tool that simulates power consumption traces from a cryptographic hardware device based on a standard textual representation of the device’s circuitry. It is much faster and less expensive to use PowerIQ in pre-silicon stage than using an oscilloscope to obtain power consumption traces from the actual physical device after it is built.
"FortifyIQ's software has the potential to dramatically reduce the cost and delay associated with the manufacturing of DPA-protected devices..." Adi Shamir, the ‘S’ in RSA and Turing prize winner who evaluated our mathematical model as well as the FortifyIQ software.
You could potentially save — in tapeout, masks, and fab run — millions of dollars and several months in your product development process.
Our innovation is a novel, patent-pending method of accurately simulating the power consumption of the designed chip. PowerIQ uses information usually available at the start of the hardware development and can be used at any phase of the hardware development cycle – RTL, post-synthesis (gate-level NetList), as well as post “place-and-route.” While we find that the most effective stage is the post syntheses (gate-level Netlist) stage, the results of the gate-level Netlist-based trace analyses can still be formulated in terms of RTL and solved at the RTL level.